1. Field
Exemplary embodiments of the present invention relate to a semiconductor fabrication technology, and more particularly, to a method for forming a dielectric layer and a capacitor in a semiconductor device.
2. Description of the Related Art
As semiconductor memory devices become highly integrated, the area of a unit memory cell and an operating voltage thereof decreases. Here, despite the reduction in a memory cell area, capacitance of, for example, 20 fF/cell or more is still desired to substantially prevent the occurrence of a soft error and a decrease in a refresh time.
To obtain an appropriate capacitance, a dielectric layer such as ZrO2/Al2O3/ZrO2 is used. However, due to the integration, it is difficult to ensure 20 fF/cell using the dielectric layer such as ZrO2/Al2O3/ZrO2 unless an effective electrode area is increased by increasing the height of a capacitor to above 1.7 μm in below 40 nm-process DRAMs.
Here, it is desirable to obtain cell capacitance of 20 fF/cell or more for below 40 nm-process DRAMs.